2013/08/22〜2015/06/16
| XO2-1200 | XO2-7000 | |
|---|---|---|
| Density LUTs | 1280 | 6864 |
| EBR RAM Blocks(9Kbits/block) | 7 | 26 |
| EBR SRAM(Kbits) | 64 | 240 |
| Dist. SRAM(Kbits) | 10 | 54 |
| User Flash Memory(Kbits) | 64 | 256 |
| PLL+DLL | 1+2 | 2+2 |
ipconfig -all
：
Physical Address. . . . . . . . . : 00-11-22-33-44-55
Done: completed successfully
//// Internal OSC setting (4.16MHz)
OSCH #( .NOM_FREQ("4.16")) IOSC
(
.STDBY(1'b0),
.OSC(clk0),
.SEDSTDBY()
);
`timescale 1ns / 1ps
module blinkled (
input rst,
output [7:0] led
);
reg [23:0] count;
//// Internal OSC setting (4.16MHz)
OSCH #( .NOM_FREQ("4.16")) IOSC
(
.STDBY(1'b0),
.OSC(clk),
.SEDSTDBY()
);
always @(posedge clk or posedge rst)
begin
if (rst)
count = 0;
else
count = count+1;
end
assign led = ~count[23:16];
endmodule
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "led[7]" SITE "107" ;
LOCATE COMP "led[6]" SITE "106" ;
LOCATE COMP "led[5]" SITE "105" ;
LOCATE COMP "led[4]" SITE "104" ;
LOCATE COMP "led[3]" SITE "100" ;
LOCATE COMP "led[2]" SITE "99" ;
LOCATE COMP "led[1]" SITE "98" ;
LOCATE COMP "led[0]" SITE "97" ;
LOCATE COMP "rst" SITE "1" ;
IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
Invalid XCF Project
xxxxxxxxxxxxxxxxxxxx/ledblink.xcf is invalid. Please correct the appropriate settings before programming.
LOCATE COMP "clk" SITE "27" ;
LOCATE COMP "oscen" SITE "32" ;
LOCATE COMP "tx" SITE "74" ;
LOCATE COMP "rx" SITE "73" ;
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// serial_probe by K.I 150527
// rxを受信すると、txからprobeの状態を2桁の16進数＋CRLFで送信
//////////////////////////////////////////////////////////////////////////////////
module serial_probe(
input clk, // 40MHz
input rst,
input rx,
output tx,
input [7:0] probe
);
reg [9:0] bcount; // baudrate counter
reg [5:0] tcount; // tx counter
reg [8:0] txbuf; // tx buffer
reg [7:0] inbuf; // input buffer
reg txf; // tx flag
//// boudrate genarator 40MHz/347 = 115274 (115200bps)
always @(posedge clk or posedge rst) begin
if (rst)
bcount <= 0; // 非同期リセット
else begin
if (bcount<346)
bcount <= bcount+1; // 1/347
else
bcount <= 0;
end
end
assign txclk = (bcount==0)?1:0; // tx UART clock
//// tx state machine
always @(posedge clk or posedge rst) begin
if (rst) begin
txf <= 0;
txbuf <= 9'b111111111;
inbuf <= 8'b00000000;
end
else if (txf & txclk) begin
if (tcount==1) begin
txbuf <= {ASCII(inbuf[7:4]),1'b0};
end
else if (tcount==11) begin
txbuf <= {ASCII(inbuf[3:0]),1'b0};
end
else if (tcount==21) begin
txbuf <= {8'h0D,1'b0}; // CR
end
else if (tcount==31) begin
txbuf <= {8'h0A,1'b0}; // LF
end
else if (tcount==41) begin // tx stop
txf <= 0;
end
else begin
txbuf <= {1'b1,txbuf[8:1]}; // tx rotation
end
end
else if (rx==0) begin // tx start by receive rx.
inbuf <= probe;
txf <= 1;
end
end
assign tx = txbuf[0];
//// tx counter
always @(posedge clk) begin
if (~txf) begin
tcount <= 0;
end
else if (txf & txclk) begin
tcount <= tcount+1;
end
end
//// HEX ASCII decoder
function [7:0] ASCII (input [3:0] in );
begin
case (in)
4'h0: ASCII = 8'h30;
4'h1: ASCII = 8'h31;
4'h2: ASCII = 8'h32;
4'h3: ASCII = 8'h33;
4'h4: ASCII = 8'h34;
4'h5: ASCII = 8'h35;
4'h6: ASCII = 8'h36;
4'h7: ASCII = 8'h37;
4'h8: ASCII = 8'h38;
4'h9: ASCII = 8'h39;
4'hA: ASCII = 8'h41;
4'hB: ASCII = 8'h42;
4'hC: ASCII = 8'h43;
4'hD: ASCII = 8'h44;
4'hE: ASCII = 8'h45;
4'hF: ASCII = 8'h46;
default:ASCII = 8'bx;
endcase
end
endfunction
endmodule
`timescale 1ns / 1ps
module ledblink (
input clk,
input rst,
output oscen,
output [7:0] led,
output tx,
input rx
);
reg [23:0] count;
serial_probe probe (
.clk(clk), // 40MHz
.rst(rst),
.rx(rx),
.tx(tx),
.probe(~led)
);
always @(posedge clk or posedge rst)
begin
if (rst)
count <= 0;
else
count <= count+1;
end
assign led = ~count[23:16];
assign oscen = 1;
endmodule
sin_table __ (.Clock( ), .ClkEn( ), .Reset( ), .Theta( ), .Sine( ));
`timescale 1ns / 1ps
module ledblink (
input clk,
input rst,
output oscen,
output [7:0] led,
output tx,
input rx
);
reg [23:0] count;
wire [7:0] theta;
wire [7:0] sine;
wire rxx;
serial_probe probe (
.clk(clk), // 40MHz
.rst(rst),
.rx(rxx),
.tx(tx),
.probe(sine)
);
sin_table tablex (
.Clock(clk),
.ClkEn(1),
.Reset(rst),
.Theta(theta),
.Sine(sine)
);
always @(posedge clk or posedge rst)
begin
if (rst)
count <= 0;
else
count <= count+1;
end
assign theta = count[23:16];
assign led = count[3:0]==0?~theta:~0; // LED明るすぎるので、暗くしている
assign oscen = 1;
assign rxx = count[15:0]==0?0:1; // sin_tableの送信タイミング
endmodule
00
02
03
05
06
08
09
0B
0C
0E
10
:
:
`timescale 1ns / 1ps
// deltasigma 150609 by K.I
module deltasigma(
input [7:0] in,
output out,
input clk,
input rst
);
parameter [11:0] MAX = 12'b000001111111; // +127
parameter [11:0] MIN = 12'b111110000001; // -127
reg [11:0] sigma;
wire [11:0] delta;
reg out;
always @(posedge clk or posedge rst) begin
if (rst) begin
sigma <= 0;
end
else begin
out <= (sigma[11]) ? 0 : 1;
sigma <= sigma + ({in[7],in[7],in[7],in[7],in} + delta);
end
end
assign delta = out?MIN:MAX; // -delta;
endmodule
`timescale 1ns / 1ps
module ledblink (
input clk,
input rst,
output oscen,
output [7:0] led,
output out,
output tx,
input rx
);
reg [23:0] count;
reg [7:0] tcount;
reg [7:0] theta;
wire [7:0] led0;
wire [7:0] sine;
serial_probe probe (
.clk(clk), // 40MHz
.rst(rst),
.rx(rx),
.tx(tx),
.probe(sine)
);
sin_table tablex ( // 正弦波テーブル
.Clock(clk),
.ClkEn(1),
.Reset(rst),
.Theta(theta),
.Sine(sine)
);
deltasigma ds1( // ΔΣ変調器
.in(sine),
.out(out),
.clk(clk),
.rst(rst)
);
//// theta counter clock 40MHz/156 = 256410 // 256kHz生成用分周器
always @(posedge clk or posedge rst) begin
if (rst)
tcount <= 0; // 非同期リセット
else begin
if (tcount<155)
tcount <= tcount+1; // 1/156
else
tcount <= 0;
end
end
assign tclk = (tcount==0)?1:0; // theta clock
always @(posedge clk or posedge rst) // 正弦波テーブル用カウンタ
begin
if (rst)
theta <= 0;
else if (tclk)
theta <= theta+1;
end
always @(posedge clk or posedge rst) // LED出力用カウンタ（意味なし）
begin
if (rst)
count <= 0;
else
count <= count+1;
end
assign led0 = count[23:16];
assign led = count[3:0]==0?~led0:~0;
assign oscen = 1;
endmodule
fc = 1/2πCR ≒ 3386
IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
IOBUF PORT "out" IO_TYPE=LVPECL33E ;
ram_table tablex (
.WrAddress(0),
.RdAddress(theta),
.Data(0),
.WE(0),
.RdClock(clk),
.RdClockEn(1),
.Reset(rst),
.WrClock(0),
.WrClockEn(0),
.Q(sine)
);
| J2-1 | J2-2 | LCD1 | LCD2 | PIN1 | PIN2 |
|---|---|---|---|---|---|
| 113 | 114 | DB7 | DB6 | LCD_DB7 | LCD_DB6 |
| 115 | 117 | DB5 | DB4 | LCD_DB5 | LCD_DB4 |
| 119 | 120 | DB3 | DB2 | ‐ | ‐ |
| GND | GND | DB1 | DB0 | ‐ | ‐ |
| 121 | 122 | E | R/W | LCD_E | LCD_RW |
| 125 | 126 | RS | Vo | LCD_RS | LCD_VO |
| 127 | 128 | VSS | VDD | LCD_VSS | LCD_VDD |
LOCATE COMP "LCD_DB[7]" SITE "113" ;
LOCATE COMP "LCD_DB[6]" SITE "114" ;
LOCATE COMP "LCD_DB[5]" SITE "115" ;
LOCATE COMP "LCD_DB[4]" SITE "117" ;
LOCATE COMP "LCD_E" SITE "121" ;
LOCATE COMP "LCD_RW" SITE "122" ;
LOCATE COMP "LCD_RS" SITE "125" ;
LOCATE COMP "LCD_VO" SITE "126" ;
LOCATE COMP "LCD_VSS" SITE "127" ;
LOCATE COMP "LCD_VDD" SITE "128" ;
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: K.I
// Module Name: lcdctrl
// Description: 1602LCD表示器のコントロール回路
// original source : http://www.cs.hiroshima-u.ac.jp/~nakano/wiki/
// オリジナルの16進数表示を、DualPortRAM上のASCII文字列を表示するように変更
// DualPortRAMのアドレスをZRA、データをZRDで制御する。resetをposiedgeに変更
// LCDの初期化回路のDelayは、clk=50MHzで設定されている。それ以下のクロックで動作可能
//////////////////////////////////////////////////////////////////////////////////
`define INIT 3'b00
`define SETPOS0 3'b01
`define SETPOS1 3'b10
`define WRITE 3'b11
module lcdctrl(clk,rst,lcd_e,lcd_rs,lcd_rw,lcd_db,ZRA,ZRD);
input clk,rst;
output lcd_e,lcd_rs,lcd_rw;
output [7:4] lcd_db;
output [4:0] ZRA;
input [7:0] ZRD;
reg lcd_e;
reg [1:0] state;
reg [4:0] crsr;
reg [3:0] addr;
reg [31:0] counter;
reg [26:0] ctrl;
wire set_enb;
wire ret;
wire [19:0] wait_cnt;
reg [7:0] ascii;
assign lcd_rw = 0;
assign ret = ctrl[26];
assign lcd_rs = ctrl[25];
assign set_enb = ctrl[24];
assign lcd_db = ctrl[23:20];
assign wait_cnt = ctrl[19:0];
always @(posedge clk or posedge rst)
if(rst) begin
addr <= 0;
counter <= 0;
state <= `INIT;
crsr <= 0;
end else if (counter<wait_cnt)
counter <= counter + 1;
else begin
counter <= 0;
if(!ret)
addr <= addr + 1;
else begin
addr <= 0;
if (state==`INIT)
state <= `SETPOS0;
else if(state==`SETPOS0 || state==`SETPOS1)
state <= `WRITE;
else if(state == `WRITE) begin
if (crsr == 15)
state <= `SETPOS1;
else if (crsr == 31)
state <= `SETPOS0;
crsr <= crsr + 1;
end
end
end
always @(posedge clk or posedge rst)
if(rst) lcd_e <= 0;
else if(set_enb && counter >= 1 && counter <= 12) lcd_e <= 1;
else lcd_e <= 0;
always @(state or addr or ascii)
case(state)
`INIT: // LCD初期化（コマンドはRS=0で行う、最後はret=1）
case(addr)
//ret+lcd_rs+set_enb,data ,wait_cnt
4'h0: ctrl = {3'b000, 4'h0, 20'hB71B0}; // wait 15ms (clk=50Mhz時)
4'h1: ctrl = {3'b001, 4'h3, 20'h320D7}; // 8bit mode / wait 4.1ms
4'h2: ctrl = {3'b001, 4'h3, 20'h01397}; // 8bit mode / wait 100us
4'h3: ctrl = {3'b001, 4'h3, 20'h00800}; // 8bit mode / wait 40us
4'h4: ctrl = {3'b001, 4'h2, 20'h00800}; // 4bit mode / wait 40us
4'h5: ctrl = {3'b001, 4'h2, 20'h00041}; // 4bit mode / wait 1us
4'h6: ctrl = {3'b001, 4'h8, 20'h00800}; // 2line mode / wait 40us
4'h7: ctrl = {3'b001, 4'h0, 20'h00041}; // / wait 1us
4'h8: ctrl = {3'b001, 4'h6, 20'h00800}; // Increment,noShift / wait 40us
4'h9: ctrl = {3'b001, 4'h0, 20'h00041}; // / wait 1us
4'hA: ctrl = {3'b001, 4'hC, 20'h00800}; // DisplayON,CursorOFF,BlinkOFF / wait 40us
4'hB: ctrl = {3'b001, 4'h0, 20'h00041};
4'hC: ctrl = {3'b101, 4'h1, 20'h1482F}; // ClearDisplay / wait 1.68ms?
default: ctrl = {3'bxxx, 4'hx, 20'hxxxxx};
endcase
`SETPOS0: // 1行目の先頭にセット
case(addr)
4'h0: ctrl = {3'b001, 4'h8, 20'h00041};
4'h1: ctrl = {3'b101, 4'h0, 20'h00800}; // Cursor=0h
default: ctrl = {3'bxxx, 4'hx, 20'hxxxxx};
endcase
`SETPOS1: // 2行目の先頭にセット
case(addr)
4'h0 : ctrl = {3'b001, 4'hC, 20'h00041};
4'h1 : ctrl = {3'b101, 4'h0, 20'h00800}; // Cursor=40h
default: ctrl = {3'bxxx, 4'hx, 20'hxxxxx};
endcase
`WRITE: // データ出力（RS=1で行う、最後はret=1）
case(addr)
4'h0 : ctrl = {3'b011, ascii[7:4], 20'h00041};
4'h1 : ctrl = {3'b111, ascii[3:0], 20'h00800};
default: ctrl = {3'bxxx, 4'hx, 20'hxxxxx};
endcase
default: ctrl = {3'bxxx, 4'hx, 20'hxxxxx};
endcase
always @(posedge clk or posedge rst)
if(rst) ascii <= 8'h20;
else if(addr == 0)
ascii <= ZRD;
assign ZRA = crsr;
endmodule
`timescale 1ns / 1ps
module ledblink (
input clk,
input rst,
output oscen,
output [7:0] led,
output LCD_E, // LCD E
output LCD_RS, // LCD RS
output LCD_RW, // LCD RW
output [7:4] LCD_DB, // LCD DB7〜4
output LCD_VO,
output LCD_VDD,
output LCD_VSS,
output tx,
input rx
);
reg [23:0] count;
wire [7:0] led0;
wire [4:0] LCD_ADRS;
wire [7:0] LCD_DATA;
serial_probe probe (
.clk(clk), // 40MHz
.rst(rst),
.rx(rx),
.tx(tx),
.probe(sine)
);
ram_table lcd_ram (
.DataInA(0),
.DataInB(0),
.AddressA(LCD_ADRS),
.AddressB(0),
.ClockA(clk),
.ClockB(clk),
.ClockEnA(1),
.ClockEnB(1),
.WrA(0),
.WrB(0),
.ResetA(0),
.ResetB(0),
.QA(LCD_DATA),
.QB()
);
// LCD module
lcdctrl blk_lcd (
.clk(clk),
.rst(rst),
.lcd_e(LCD_E),
.lcd_rs(LCD_RS),
.lcd_rw(LCD_RW),
.lcd_db(LCD_DB),
.ZRA(LCD_ADRS),
.ZRD(LCD_DATA)
);
assign LCD_VSS = 0;
assign LCD_VDD = 1;
assign LCD_VO = 0;
always @(posedge clk or posedge rst)
begin
if (rst)
count <= 0;
else
count <= count+1;
end
assign led0 = count[23:16];
assign led = count[3:0]==0?~led0:~0;
assign oscen = 1;
endmodule
→lcd_data.memの内容がちゃんと表示されている
| J2-1 | J2-2 | J4-1 | J4-2 | J3-1 | J3-2 | J5-1 | J5-2 | |||
|---|---|---|---|---|---|---|---|---|---|---|
| NC | VCCIO0 | 3.3V | VCCIO3/4/5 | 1.2V | VCCIO1 | NC | VCCIO2 | |||
| 109(DONE) | 110(INIT) | 3.3V | NC | 1.2V | NC | 71(SI,R39*) | 69(R37*) | |||
| 111 | 112 | 1 | 2 | 74(TX*) | 73(RX*) | 70(SN,R39*) | 68(R37*) | |||
| GND | GND | 3 | 4 | 76(CTS*) | 75(RTS*) | 67(R35*) | 62(R33*) | |||
| 113 | 114 | 5 | 6 | GND | GND | 65(R35*) | 61(R33*) | |||
| 115 | 117 | 9 | 10 | 78(DCD*) | 77(DSR*) | GND | GND | |||
| 119(PROGn) | 120(JTAGen) | GND | GND | 82 | 81(DTR*) | 60(R31*) | 58(R29*) | |||
| GND | GND | 11 | 12 | GND | GND | 59(R31*) | 57(R29*) | |||
| 121 | 122 | 13 | 14 | 84 | 83 | GND | GND | |||
| 125(SDA) | 126(SCL) | GND | GND | 86 | 85 | 56(R41*) | 54(R40*) | |||
| 127 | 128 | 19 | 20 | GND | GND | 55(R41*) | 52(R40*) | |||
| GND | GND | 21 | 22 | 92 | 91 | GND | GND | |||
| 130(TMS) | 131(TCK) | GND | GND | 94 | 93 | 50(R38*) | 48(R36*) | |||
| 132 | 133 | 23 | 24 | GND | GND | 49(R38*) | 47(R36*) | |||
| 136(TDI) | 137(TDO) | 25 | 26 | 96 | 95 | GND | GND | |||
| GND | GND | GND | GND | 98(LED1) | 97(LED0) | 45(SO,R34*) | 43(R32*) | |||
| 138 | 139 | 27(X2_CLK*) | 28 | GND | GND | 44(MCLK,R34*) | 42(R32*) | |||
| 140 | 141 | GND | GND | 100(LED3) | 99(LED2) | GND | GND | |||
| 142 | 143 | 32(X2_EN*) | 33 | 105(LED5) | 104(LED4) | 41(R30*) | 39(R28*) | |||
| GND | GND | 34 | 35 | 107(LED7) | 106(LED6) | 40(CSSPIN,R30*) | 38(R28*) |