2011/05/06〜
NET "clk" LOC = "P37" ;
NET "clrn" LOC = "P27" ;
NET "d<0>" LOC = "P2" ;
NET "d<1>" LOC = "P8" ;
NET "d<2>" LOC = "P44" ;
NET "d<3>" LOC = "P6" ;
NET "d<4>" LOC = "P43" ;
NET "d<5>" LOC = "P5" ;
NET "d<6>" LOC = "P42" ;
NET "d<7>" LOC = "P3" ;
NET "dac<0>" LOC = "P21" ;
NET "dac<1>" LOC = "P20" ;
NET "dac<2>" LOC = "P19" ;
NET "dac<3>" LOC = "P18" ;
NET "dac<4>" LOC = "P15" ;
NET "dac<5>" LOC = "P14" ;
NET "dac<6>" LOC = "P13" ;
NET "dac<7>" LOC = "P12" ;
NET "dac<8>" LOC = "P10" ;
NET "dac<9>" LOC = "P11" ;
NET "gain" LOC = "P28" ;
NET "ldacn" LOC = "P25" ;
NET "led" LOC = "P31" ;
NET "pdn" LOC = "P22" ;
NET "rstn" LOC = "P23" | PULLUP ;
NET "rx" LOC = "P35" ;
NET "tx" LOC = "P34" ;
NET "wrn" LOC = "P30" ;
NET "to" LOC = "P33" ;
`timescale 1ns / 1ps
module mini_cpld(
input clk,
output reg led,
input rx,
output tx,
inout [7:0] d,
input [7:0] adc,
output adcc,
output adcp,
output adcs,
output reg [7:0] dac,
output dacs,
output reg dacw
);
reg [23:0] count;
always @(posedge clk) begin
if (!count) begin
led <= ‾led;
end
count <= count+1;
end
endmodule
module xxx_serial(
input clk,
input rstn,
output reg to,
input rx,
output tx,
inout [7:0] d,
output [9:0] dac,
output ldacn,
output wrn,
output clrn,
output gain,
output led,
output pdn
);
reg [5:0] bcount; // baudrate counter
reg [5:0] tcount; // tx counter
reg [8:0] txbuf;
reg txf; // tx flag
reg [3:0] count; // Serial counter
reg [15:0] buff; // Serial buffer
reg [9:0] vout; // 10bit DAC buffer
reg dacw;
wire cko,ckf,tco,rst;
always @(posedge clk) begin
if (bcount==43) begin
bcount <= 0;
end
else begin
bcount <= bcount+1;
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
txf <= 0;
txbuf <= 9'b111111111;
end
else if (txf==1 && bcount==0) begin
if (tcount==1) begin
txbuf <= {4'b0011,1'b0,to,vout[9:8],1'b0};
end
else if (tcount==11) begin
txbuf <= {4'b0011,vout[7:4],1'b0};
end
else if (tcount==21) begin
txbuf <= {4'b0011,vout[3:0],1'b0};
end
else if (tcount==31) begin
txbuf <= {8'h0D,1'b0};
end
else if (tcount==41) begin
txf <= 0;
end
else begin
txbuf <= {1'b1,txbuf[8:1]};
end
end
else if (rx==0) begin
txf <= 1;
end
end
always @(posedge clk) begin
if (!txf) begin
tcount <= 0;
end
else if (txf && bcount==0) begin
tcount <= tcount+1;
end
end
always @(posedge cko or posedge rst) begin
if (rst) begin
buff <= 0;
dacw <= 1;
vout <= 0;
end
else begin
if (ckf) begin
if (count==7) begin // 8bit - 1frame
vout <= {buff[7:1],3'b000};
to <= buff[0];
end
else if (count==15) begin // 16bit - 1frame
vout <= {~buff[15],buff[14:6]};
to <= buff[5];
end
count <= 0;
dacw <= 0; // DAC WR set
end
else begin
dacw <= 1; // DAC WR clear
count <= count+1;
end
buff <= {buff[14:0],tco}; // Serial-Parallel convert
end
end
assign rst = ~rstn;
assign cko = ~d[1];
assign ckf = ~d[3];
assign tco = ~d[5];
assign ldacn = 0; // DAC ldac enable
assign pdn = 1; // DAC pd disable
assign clrn = 1; // DAC clr disable
assign gain = 0; // DAC gain 0-Vref
assign wrn = dacw; // DAC write
assign dac = vout; // 10bit -> 10bit
assign led = ~to;
assign tx = txbuf[0];
endmodule